The present invention relates to integrated circuits and, more particularly, to a clock delay compensation circuit for an integrated circuit having two or more voltage domains.
High performance integrated circuits, such as sub-100 nm ASICs (Application Specific Integrated Circuits) for portable, wireless applications employ complex techniques to extract maximum performance out of the ASICs. In addition to the requirement for high performance, there is a requirement for very low power consumption. One technique to achieve low power consumption is to use multiple voltage domains within a single integrated circuit (IC), where each voltage domain is served by independent power supplies, which enable applications to vary the supply in order to maximize power savings without affecting performance. These multiple voltage domain systems also have to overcome any effects caused by voltage transitions.
Since the different domains are served by independent power supplies that can also change, it is normal to expect that at any point in time the different domains may be at different operational voltages. This poses a significant challenge to designers to achieve clock balancing across the multiple domains because the moment the voltage of a domain is changed, the associated delays in the clock path also change. Such clock skew can cause operational errors.
Accordingly, there is a need for a clock delay compensation circuit for high performance ICs that have multiple voltage domains.